1. Field of the Invention
The present invention relates to an electro-static discharge (ESD) protection element for preventing a high current from flowing and preventing breakage even when a battery is connected with reverse polarity by mistake.
2. Description of the Related Art
As a conventional input circuit for a semiconductor integrated circuit (hereinafter, referred to as IC), a circuit as illustrated in FIG. 4 has been known (see, for example, Japanese Patent Application Laid-open No. Hei 7-153846 (FIG. 1)).
The IC includes a positive (plus) power supply terminal 121, a negative (minus) power supply terminal 122, and at least one input terminal 120. The positive power supply terminal 121 is connected to a plus terminal of a battery 101 and the negative power supply terminal 122 is connected to a minus terminal of the battery 101. Between the input terminal 120 and the negative power supply terminal 122, a main ESD protection circuit 100 is normally disposed in the vicinity of a pad of the IC.
An internal circuit (inverter) 130 that receives a signal of the input terminal 120 is provided. As charged device model (CDM) measures for protecting a gate thereof from electro-static discharge (ESD), an ESD protection circuit 110 is disposed near the internal circuit 130. The ESD protection circuit 110 includes an N-channel transistor 11, a P-channel transistor 13, and a resistor 15. Drains of the N-channel transistor 11 and the P-channel transistor 13 are connected to the gate of the internal circuit 130. A gate, a source, and a substrate of the N-channel transistor 11 are connected to VSS. A gate, a source, and a substrate of the P-channel transistor 13 are connected to VDD. The N-channel transistor 11 and the P-channel transistor 13 are in an OFF state (high impedance state). In a normal operating state, the presence or absence of the N-channel transistor 11 and the P-channel transistor 13 does not affect the operation of the internal circuit. The resistor 15 for ESD protection may be a resistor having a given value (for example, about 1 kΩ) interposed by design, or may be a parasitic resistance of wiring of the IC.
In a CDM, in the state in which the IC is charged to a high voltage, when the voltage is discharged from the input terminal 120, electric charges of the internal circuit 130 on the substrate side are generally discharged rapidly via the substrate and the main ESD protection circuit 100. On the other hand, electric charges of the gate of the internal circuit 130 are discharged slowly because of the resistor 15. As a result, a high voltage is applied instantaneously between the gate and the substrate of the internal circuit 130, and the breakage of the gate of the internal circuit may occur. In order to prevent the breakage, the OFF transistors 11 and 13 are interposed between the gate of the internal circuit and the positive power supply terminal 121 and the negative power supply terminal 122, respectively, so that the OFF transistors 11 and 13 are broken down before a high voltage is applied between the gate of the internal circuit and the respective power supply terminals. In this way, the gate of the internal circuit can be prevented from being applied with a high voltage, and the breakage in the CDM can be prevented.
Note that, reference symbols 11D and 13D represent parasitic diodes of the N-channel transistor 11 and the P-channel transistor 13, respectively.
FIG. 5 illustrates an example of an image diagram of IC layout. There are three pads of a VDD PAD connected to the VDD terminal, an IN PAD connected to the IN terminal, and a VSS PAD connected to the VSS terminal. In the vicinity of the IN PAD, the main ESD protection circuit 100 is laid out. The internal circuit 130 is laid out inside the IC, and, in the vicinity thereof, the ESD protection circuit 110 for CDM measures is laid out.
FIG. 5 illustrates only three pads, but a normal IC includes a larger number of pads and circuits.
The conventional protection circuit, however, has the following problem. When the battery is connected with reverse polarity, the parasitic diodes of the respective ESD protection elements are biased in the forward direction, and a current flows to generate heat.